An efficient BIST method for testing of embedded SRAMs

We have developed an algorithm by which to enable conventional microprocessors to test their on-chip SRAM using their existing hardware and software resources. This test method utilizes a mixture of existing memory testing techniques, which cover all important memory faults. This i; achieved by writing a routine called BIST Program by which only uses the existing ROM and creates no additional hardware overhead. BIST program implements the "length 9N' test algorithm. The proposed test algorithm covers 100% of faults under the fault mdel plus a data retention test. Memory faults diagnostic capability is also provided by BIST program. This method can be implemented for embedded SRAM testing of all microprocessors, microcontrollers and DSPs. This test algorithm is experimented on 32K SRAM 16-Bit of Texas Instruments TMS320C548 DSP.